Renesas推出雙核32-bit SuperH微控制器擁有960-MIPS操作性能和800 MFLOPS浮點操作性能 為消費者、工業、汽車音頻/導航和多媒體應用提供的多用途設備包括：兩個SH2A-FPU CPU核和全面的外圍功能 瑞薩科技美國有限公司宣布五項新SuperH®32比特微控制器，可用于多核技術達到高級性能以滿足許多內嵌系統的應用，如消費產品、工業設備和汽車音頻和導航系統。SH7205 和 SH7265設備公司全并兩個超標量體系結構的SH2A-FPU CPU核和一套片上外置設備，包括USB, ATAPI和圖像處理功能。當雙核微控制器在200 MHz最大操作頻率情況下操作時，每一個CPU在Dhrystone v1.1基準操作性能下每秒執行4.8億條指令，每秒執行4億個浮點操作。 為滿足必然的高功能和性能需求，新型微控制器使用接近基礎而不同于傳統方法的設計。在過去，過程節點用于提高密度整合和提高操作速度。今天，半導體技術已經達到可以利用相當可觀的時間開發更好的制造過程節點。此外，現在的設計的解決方案用于解決各種難題，如增強的電流漏露率。 為避免這些問題，瑞薩針對在嵌入式應用中使用的微控制器開發了多核體系。其中一個主要的好處，就是在單芯片上植入多核CPU，由于CPU核可平行執行軟件編碼。針對內嵌式系統的多核IC被提前引進，主要應用于圖像處理和相似多媒體產品的重載處理。相反地，SH7205和SH7265微控制器是多用途設備，目標瞄準在大范圍要求高速即時控制應用上，處理性能等同于數字信號處理器芯片。 多核架構 SH7205和SH7265微控制器的多核體系在提供靈活性的同時盡可能地使性能達到高級。微控制器在過程性能不能退化且過程變得復雜和快速時，微控制器執行解決方案。應用在CPU核中的三個主要技術是： 國內使用單個特殊CPU多層體系架構的公交汽車系統。4層架構2層用于CPU的使用，別外兩層用于DMAC使用。當公共汽車在使用另一個CPU的時候阻止了時間的浪費達到高速即時處理。 CPU核可處理不同的操作系統（OSs）或是在同一個上操作。如果一個CPU核正在運行µITRON OS，其它在運行µClinux OS，如他們可執行不同的程序。這種性能可使工程師們根據自己的操作狀態和數據需要把系統變的更具靈活性。 CPU雙核可直接與另外一個通話。每一個CPU可以檢查另一個的狀態，他們可以根據自己的需要利用記憶改變數據。因此，處理聯接可通過共同調換他們各自的狀態和數據在CPU之間執行。 芯片上的外圍功能 外圍功能的廣泛排列，被植入在了SH7205和SH7265芯片中，減少了外部零件的需要，在利用最小成本的情況下創建高性能系統。包括：高速2.0USB標準接口，ATAPI接口和其它各種接口。設備擁有一個2D圖形引擎和一個為用于圖片處理的數字化音頻輸入端，以及用于圖像輸出和音頻輸出處理的類似RGB的WQVA （480x234-pixel）和QVA （320x240-pixel）輸出端。 其它片上功能包括適用于電機控制系統的5-頻道多功能記時器，雙CAN控制器，8頻道10比特A/D轉換器，2頻道8比特D/A轉換器，監視時鐘，針對速度提升音頻應用的具備2空間容量的14頻道DMAC等等。 除這些功能之外，SH7265針對AAC提供編碼加速器用音頻數據壓縮。這種功能可以用于高速運行硬件或是類似AAC文檔的創新。 original text [COLOR=#708090]Renesas Introduces Dual-core 32-bit SuperH Microcontrollers Capable of Up to 960-MIPS Processing Performance, 800 MFLOPS Floating-point Operation Performance General-purpose devices have two SH2A-FPU CPU cores and comprehensive peripheral functions for consumer, industrial, car audio/navigation, and multimedia applications. Renesas Technology America, Inc. today announced five new SuperH® 32-bit microcontrollers that use multi-core technology to achieve the high levels of performance required by many embedded system applications such as consumer products, industrial equipment, and car audio and navigation systems. The SH7205 and SH7265 devices incorporate two superscalar SH2A-FPU CPU cores and a comprehensive set of on-chip peripherals that includes USB, ATAPI, and image processing engine functions. When the dual-core microcontrollers are operating at their 200 MHz maximum operating frequency, each CPU delivers 480-MIPS （million instructions per second） processing performance in the Dhrystone v1.1 benchmark, and 400-MFLOPS （mega floating point number operations per second） floating-point operation performance. To meet inevitable demands for higher functionality and performance, the new microcontrollers use a design approach fundamentally different from the traditional method. In the past, generations of ever-finer process nodes have been used to improve integration density and increase operating speed. Today, however, semiconductor technology has reached the point where it takes considerable time to develop finer manufacturing process nodes. Moreover, fundamental limits of physics now mandate design solutions for an expanding variety of difficult problems, such as increased leakage current. To avoid these problems, Renesas developed a multi-core architecture for microcontrollers used in embedded applications. One of the main benefits of putting multiple CPU cores in a single chip is increased device performance because the CPU cores can execute lines of software code in parallel. The multi-core ICs for embedded systems previously introduced mostly have been aimed at image processing and similar multimedia products with heavy processing loads. By contrast, the SH7205 and SH7265 microcontrollers are general-purpose devices that target a broad span of applications requiring high-speed real-time control and processing performance equivalent to that of a digital signal processor （DSP） chip. Multi-core architecture The multi-core architecture of the SH7205 and SH7265 microcontrollers makes it possible to achieve high levels of performance while offering flexibility of use. The microcontrollers implemented a solution in which real-time processing performance does not degrade as processing becomes more complex and faster. The three main technologies in the CPU core’s design are: • The internal bus system uses a CPU-specific multi-layer structure. A 4-layer configuration provides two layers for CPU use and two for DMAC （direct memory access controller） use. This prevents time from being wasted while the bus is in use by the other CPU, for high-speed real-time processing. • The CPU cores can operate on different operating systems （OSs） or the same one. If one CPU core runs the µITRON OS, while the other runs the µClinux OS, for example, they can execute completely different programs. This capability lets engineers construct a system flexibly, according to its use or purpose. • The two CPU cores can communicate directly with each other. Each CPU can check the status of the other one, and they can exchange data using memory provided for that purpose. Thus, processing linkage can be implemented between the CPUs through mutual exchanges of their respective processing states and data. On-chip peripheral functions The extensive array of peripheral functions built into the SH7205 and SH7265 chips reduces the need for external parts and enables to create high-performance systems at less cost. They include a USB v2.0 High-Speed （480-Mbps） specification interface, ATAPI interface, and other various interfaces. The devices have a 2D graphic engine and a digital video input pin for graphic processing, and has WQVA-size （480x234-pixel） and QVA-size （320x240-pixel） analog RGB output pins for image and video output processing. Other on-chip functions include a 5-channel multifunction timer unit （MTU） suitable for motor control systems, 2-channel CAN controller, 8-channel 10-bit A/D converter, 2-channel 8-bit D/A converter, watchdog timer （WDT）, 14-channel DMAC with 2-dimensional addressing capability for speeding up video applications, and more. Besides these functions, the SH7265 provides an encoding accelerator for AAC （Advanced Audio Coding） as the audio data compression method. This function can be used for high-speed hardware implementation of music data or similar AAC file creation.[/color]